CVEvulnerability

CVE-2019-17391

4.6 MEDIUM Published 2019-11-14 Modified 2026-06-17 Official page ↗
Status
Modified
Published
2019-11-14
Last modified
2026-06-17
Assigner
[email protected]
CVSS 3.1 ([email protected])
4.6 MEDIUM — CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CVSS 2.0 ([email protected])
2.1 LOW — AV:L/AC:L/Au:N/C:P/I:N/A:N
Weaknesses
CWE-755

Description

An issue was discovered in the Espressif ESP32 mask ROM code 2016-06-08 0 through 2. Lack of anti-glitch mitigations in the first stage bootloader of the ESP32 chip allows an attacker (with physical access to the device) to read the contents of read-protected eFuses, such as flash encryption and secure boot keys, by injecting a glitch into the power supply of the chip shortly after reset.

Affected configurations

• espressif esp32-d0wd firmware • espressif esp32-d2wd firmware • espressif esp32-s0wd firmware • espressif esp32-pico-d4 firmware

Related

Weakness · CWE (1)

  • CWE-755 Improper Handling of Exceptional Conditions weakness

Referenced by CWE · observed example (2)

  • CWE-1247 Improper Protection Against Voltage and Clock Glitches weakness
  • CWE-1384 Improper Handling of Physical or Environmental Conditions weakness

References