CVEvulnerability
CVE-2025-45006
9.1 CRITICAL
Official page ↗
- Status
- Deferred
- Published
- 2025-07-01
- Last modified
- 2026-06-17
- Assigner
- [email protected]
- CVSS 3.1 (134c704f-9b21-4f2e-91b3-4a467353bcc0)
- 9.1 CRITICAL — CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
- Weaknesses
- CWE-266
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
Related
Weakness · CWE (1)
- CWE-266 Incorrect Privilege Assignment weakness
References
- https://github.com/chipsalliance/rocket-chip.git github.com
- https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md github.com
- https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications lf-riscv.atlassian.net