CVEvulnerability

CVE-2025-54515

1.0 LOW Published 2025-11-23 Modified 2026-10-18 Official page ↗
Status
Deferred
Published
2025-11-23
Last modified
2026-10-18
Assigner
[email protected]
CVSS 4.0 ([email protected])
1.0 LOW — CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
Weaknesses
CWE-1284

Description

The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.

Related

Weakness · CWE (1)

  • CWE-1284 Improper Validation of Specified Quantity in Input weakness

References