CAPEC-663 Exploitation of Transient Instruction Execution

An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.

1. [Explore] [Survey target application and relevant OS shared code libraries] Adversary identifies vulnerable transient instruction sets and the code/function calls to trigger them as well as instruction sets or code fragments (gadgets) to perform attack. 2. [Explore] [Explore cache and identify impacts] Utilize tools to understand the impact of transient instruction execution upon address spaces and CPU operations. 1. [Experiment] [Cause conditions for identified transient instruction set execution] Adversary ensures that specific code/instructions of the target process are executed by CPU, so desired transient instructions are executed. 2. [Experiment] [Cause specific secret data to be cached from restricted address space] Executed instruction sets (gadgets) in target address space, initially executed via adversary-chosen transient instructions sets, establish covert channel and transfer secret data across this channel to cache. 1. [Exploit] [Perform covert channel attack to obtain/access secret data] Adversary process code removes instructions/data from shared cache set, waits for target process to reinsert them back into cache, to identify location of secret data via a timing method. Adversary continuously repeat this process to identify and access entirety of targeted secret data.

• The adversary needs at least user execution access to a system and a maliciously crafted program/application/process with unprivileged code to misuse transient instruction set execution of the CPU.

• [High] Detailed knowledge on how various CPU architectures and microcode perform transient execution for various low-level assembly language code instructions/operations. • [High] Detailed knowledge on compiled binaries and operating system shared libraries of instruction sequences, and layout of application and OS/Kernel address spaces for data leakage.

• Confidentiality: Read Data • Access Control: Bypass Protection Mechanism • Authorization: Execute Unauthorized Commands

• Implementation: DAWG (Dynamically Allocated Way Guard) - processor cache properly divided between different programs/processes that don't share resources • Implementation: KPTI (Kernel Page-Table Isolation) to completely separate user-space and kernel space page tables • Configuration: Architectural Design of Microcode to limit abuse of speculative execution and out-of-order execution • Configuration: Disable SharedArrayBuffer for Web Browsers • Configuration: Disable Copy-on-Write between Cloud VMs • Configuration: Privilege Checks on Cache Flush Instructions • Implementation: Non-inclusive Cache Memories to prevent Flush+Reload Attacks